It is well known in the art to use duplicated systems. Canadian Pat. No. 876,366 dated July 20, 1971 to R. W. Downing; J. S. Nowak; F. F. Taylor, and W. Ulrich depicts a duplicated system comprising two "central controls", a memory system comprising a plurality of independent memories, and a plurality of independent transmission paths; these component parts are then arranged into two independent (i.e. duplicated) combinations. Each combination comprises one of the "central controls", selected ones of the independent memories, and selected ones of the independent transmission paths (see pages 3 and 4 of the aforementioned Canadian patent).
Canadian Pat. No. 876,366 states that: "It is a feature of this invention that since the transmission paths are selectively connectable to both central controls and to each of the plurality of independent memories, it is possible to provide an operable combination of central control, memory, and transmission paths even though multiple troubles may exist in the overall data processing system. Furthermore, . . . the first and the second central controls concurrently perform identical work functions, . . . " (page 4, lines 12 to 20).
U.S. Pat. No. 3,768,074 dated Oct. 23, 1973 to R. S. Sharp and H. P. Birchmeler depicts a system which "includes a plurality of processing groups each including a processing unit, an I/O control unit and the like, which groups may be partitioned into separate subsystems, each subsystem including at least one processing group". (Column 2, lines 61 to 65.) The patent continues to state at column 3, lines 3 to 13, "Features of the present invention reside in a plurality of representative unis provided for each of the processing groups which representative units receive system configuration codes specifying the particular sub-system to which the processing groups are to be joined. Each representative unit transmits its own system configuration code to all the other representative units and receives system configuration codes in turn. In this manner, processing groups having been assigned the same system configuration codes will then be joined as a subsystem."
U.S. Pat. No. 3,633,175 dated Jan. 4, 1972 by S. D. Harper depicts "a novel memory access construction in which a memory that initially has defective storage locations is associated with a set of auxiliary storage locations. Where the memory is fabricated as an integrated circuit on a semiconductor chip, the auxiliary locations can be in the same chip, or in different, and also partly defective, chips. A content addressable memory (CAM) is provided having an argument section with a number of locations, each of which is capable of storing the address of one defective location in the main memory. The content addressable memory also has a function section in which, for each address that can be stored in the argument section, there is a corresponding memory location for storing the address of an auxiliary location." (Column 1, lines 49 to 61.) This patent continues to state at column 1, lines 69 to 75, "When the CAM determines that the address currently in the memory address register is the same as an address in the argument section, i.e. is the address of a defective main memory location, the CAM supplies, from its function section, an auxiliary address to the address decoder driver. This directs the information exchange to a spare address location that has been assigned to that defective main memory location."